ANA_CLK_RTC_SEL=SLOW_CK, FAST_CLK_RTC_SEL=XTAL_DIV_4, SOC_CLK_SEL=XTAL, CK8M_DIV=DIV128, ENB_CK8M_DIV=CK8M_DIV_256
| CK8M_DIV | CK8M_D256_OUT divider. 00: div128 01: div256 10: div512 11: div1024. 0 (DIV128): DIV128 1 (DIV256): DIV256 2 (DIV512): DIV512 3 (DIV1024): DIV1024 |
| ENB_CK8M | disable CK8M and CK8M_D256_OUT |
| ENB_CK8M_DIV | 1: CK8M_D256_OUT is actually CK8M 0: CK8M_D256_OUT is CK8M divided by 256 0 (CK8M_DIV_256): CK8M_DIV_256 1 (CK8M): CK8M |
| DIG_XTAL32K_EN | enable CK_XTAL_32K for digital core (no relationship with RTC core) |
| DIG_CLK8M_D256_EN | enable CK8M_D256_OUT for digital core (no relationship with RTC core) |
| DIG_CLK8M_EN | enable CK8M for digital core (no relationship with RTC core) |
| CK8M_DFREQ_FORCE | |
| CK8M_DIV_SEL | divider = reg_ck8m_div_sel + 1 |
| XTAL_FORCE_NOGATING | XTAL force no gating during sleep |
| CK8M_FORCE_NOGATING | CK8M force no gating during sleep |
| CK8M_DFREQ | CK8M_DFREQ |
| CK8M_FORCE_PD | CK8M force power down |
| CK8M_FORCE_PU | CK8M force power up |
| SOC_CLK_SEL | SOC clock sel. 0: XTAL 1: PLL 2: CK8M 3: APLL 0 (XTAL): XTAL 1 (PLL): PLL 2 (CK8M): CK8M 3 (APLL): APLL |
| FAST_CLK_RTC_SEL | fast_clk_rtc sel. 0: XTAL div 4 1: CK8M 0 (XTAL_DIV_4): XTAL_DIV_4 1 (CK8M): CK8M |
| ANA_CLK_RTC_SEL | slow_clk_rtc sel. 0: SLOW_CK 1: CK_XTAL_32K 2: CK8M_D256_OUT 0 (SLOW_CK): SLOW_CK 1 (CK_XTAL_32K): CK_XTAL_32K 2 (CK8M_D256_OUT): CK8M_D256_OUT |